Logic Card A10/A1 5 Test Theory. - TM-9-4931-363-14-P0061

9-4931-363-14&P

J8-8 to energize the remaining part of the voltage divider

K3. The 28 volts is connected from contact 2 of S8-A to

network on the logic card. J8-4 provides the signal return.

K3-4, which causes K3 to latch. K3-2 and -1 apply a ground

The test signal B (test signal Pi) output at J8-7 is connected

to indicators DS14 through DS17. Refer to the logic card

through contact 3 and wiper 1 of S8-1, and through the

schematic from TM 9-1270-212-14&P. With the fail enable

previously discussed contacts of S4-1, S9, and S5-A, to the

input at J8-24 held low and the BIT initiate input at J8-9

meter input and to the phase-sensing input of the A2 card.

held high, the four indicator outputs at J8-13, -20, -14, and

-23 of the logic card are open.

(9) Refer to step 8 in figure 2-9 and in the logic card

test table. Setting S9 to position R3 connects the test signal

(3) Refer to step 2 in figure 2-9 and in the logic card

D (test signal Gk) output at J8-5 through contact 3 and

test table. When S11 is released, K3 remains latched, 28

wiper 1 of S8-J, through contact 7 and wiper 1 of S4-H,

volts dc is removed from J8-9, and the ground at J8-24 is

and through the previously discussed contacts of S9 and

removed. The TR3 comparator output at J8-33 is grounded

S5-A, to the meter input and to the phase-sensing input of

through contact 2 and wiper 1 of S8-B. The go-latch-not

the A2 card.

output at J8-26 is grounded through contact 2 and wiper 1

of S8-K. With the inputs to the logic card as specified, the

(10) Refer to step 9 in figure 2-9 and in the logic

go output at J8-13 and the EIA output at J8-23 are both 28

card test table. Setting S8 to position 3 maintains the same

volts, lighting DS14 and DS17 on the test set.

basic conditions described in step 1. The ground

(4) Refer to step 3 in figure 2-9 and in the logic card

connections are removed from J8-27 and -28. With S11

pressed, energized relays K3 and K8 provide grounds as

test table. The 10 volts ac, in phase, is connected to J8-11

discussed in paragraph (6).

to energize part of the voltage divider network on the logic

card. J8-4 provides a signal return. The test signal A (test

(11) Refer to step 10 in figure 2-9 and in the logic

signal Pj) output at J8-2 is connected through contact 2 and

wiper 1 of S8-1, through contact 7 and wiper 1 of S4-1,

card test table. When S11 is released, K3 again remains

latched, 28 volts dc is removed from J8-9, and the ground

through S9-2 and -3, and through contact 2 and wiper 1 of

at J8-24 is removed. The power fail input at J8-31 is

S5-A to the meter input, and through contact 8 and wiper 2

grounded through contact 4 and wiper 1 of S8-B. With

of S4-A to the phase-sensing input to the A2 card.

these inputs to the logic card, the pilot linkage output at

(5) Refer to step 4 in figure 2-9 and in the logic card

J8-20 and EIA output at J8-23 are each 28 volts, lighting

test table. Setting S9 to position R3 connects the test signal

DS16 and DS17 on the test set.

C (test signal TR) output at J8-3 through contact 2 and

wiper 1 of S8-J, through contact 7 and wiper 1 of S4-H,

NOTE

and through S9-1 and -3 to the meter and phase detector as

in (3) above.

The information in (12) and (13) below applies

to logic card A15, used in the EIA from

(6) Refer to step 5 in figure 2-9 and in the logic card

XM136, only. P1-15 and -17 of logic card A10,

test table. Setting S8 to position 2 maintains the same basic

used in the EIA from XM128, are not

connections described in step 1. The ground connections

connected.

are removed from J8-33 and -26. With S11 pressed, K8

energizes and again provides a ground at J8-24. K3 also

(12) Refer to step 11 in figure 2-9 and in the A15

energizes to provide grounds for indicators DS14 through

test table. The connections for the out-of-phase 10 volts ac

DS17.

and for the signal return are the same as in (7) above, as are

the connections for S5, A2, and DS19 and DS20. The test

(7) Refer to step 6 in figure 2-9 and in the logic card

signal Gj output from the logic card into J8-15 is connected

test table. When S11 is released, K3 remains latched, 28

to the meter through contact 4 and wiper 1 of S8-1,

volts dc is removed from J8-9, and the ground at J8-24 is

through contact 7 and wiper 1 of S4-H, and through

removed. The skip-not output at J8-27 is grounded through

contact 2 of S9 in the R2 position.

contact 3 and wiper 1 of S8-K. The relay drive 5 input at

J8-28 is grounded through contact 3 and wiper 1 of S8-B.

(13) Refer to step 12 in figure 2-9 and in the A15

With these inputs to the logic card, the go output at J8-13

test table. The connections for this step are the same as for

and gunner linkage output at J8-14 are each 28 volts, which

(12) above except that test signal Gi from logic card A15 is

lights DS14 and DS15 on the test set.

connected to the meter through J8-17, through contact 4

and wiper 1 of S8, and through contact 1 of S9 in the R3

(8) Refer to step 7 in figure 2-9 and in the logic card

position.

test table. The 10 volts ac, out of phase, is connected to

2-45