Quantcast Logic Card A10/A1 5 Test Theory. - TM-9-4931-363-14-P0055

 

Click here to make tpub.com your Home Page

Page Title: Logic Card A10/A1 5 Test Theory.
Back | Up | Next

Click here for thousands of PDF manuals

Google


Web
www.tpub.com

Home


   
Information Categories
.... Administration
Advancement
Aerographer
Automotive
Aviation
Construction
Diving
Draftsman
Engineering
Electronics
Food and Cooking
Logistics
Math
Medical
Music
Nuclear Fundamentals
Photography
Religion
   
   

 

Share on Google+Share on FacebookShare on LinkedInShare on TwitterShare on DiggShare on Stumble Upon
Back
Figure 2-7. Buffer amplifier module test functional diagram
Up
TM-9-4931-363-14-P Fire Control Subsystem Test Set AN/GSM-249 P/N 2201736-05 Manual
Next
Figure 2-8. Sequencer card A9 test functional diagram (sheet 1 of 5)
TM
9-4931-363-14&P
(9) Refer to step 8 in figure 2-8 and in the A9 test
(4) Refer to step 3 in figure 2-8 and in the A9 test
table. When S11 is released, K8 deenergizes and the reset
table. With all switches set for step 2, changing the
signal at J7-6 goes high. Since the skip function is enabled,
oscilloscope time base enables the first enable-B signal to be
the count skips to U10-7 and the signals at relay drives 5
displayed.
through 9 are grounded, one at a time, to light test set
indicators DS8, DS9, DS10, DS11, and DS12 in sequence,
(5) Refer to step 4 in figure 2-8 and in the A9 test
about five indicators a second. DS8 and DS13 remain
table. Indicators DS8 and DS13 will be lighted for steps 1,
lighted as explained above.
2, and 3. With 5 volts dc connected at J7-1, and the SKIP,
GO LATCH, and PWR FAIL LATCH inputs at J7-24, -13,
and -11 grounded through S8-B, the open RESET signal
(10) Refer to step 9 in figure 2-8 and in the A9 test
input at J7-6 enables the logic circuitry to count. Refer to
table. With the card logic set at the end of step 8 as
the A9 foldout schematic from TM 9-1270-212-14&P. The
explained in (9), applying 28-volt power to J7-18 energizes
circuitry counts until U10-13 goes low. As described in step
relays K1 and K2 on the card. The 5-volt power applied to
1, the low at U10-13 is connected to U4-7 and -10 where it
J7-1 is also applied to J7-33 and J7-27. The 5 volts is
inhibits counter U4. The low at U10-13 is also connected to
connected through energized contacts 7 and 6, and 2 and 1
U3-5 which causes U3-6 to go low. The low is connected
of K1 and through R14 to the base of Q4 in the test set. Q4
through J7-26 to Q1 in the test set where it turns Q1 on,
conducts, turning on DS4. The 5 volts is also connected
causing DS13 to light. During the count when U10-7 goes
through energized contacts 7 and 6, and 2 and 1 of K2 and
low, the low at U3-9 causes U3-11 to go low. The low is
through R15 to the base of Q2. Q2 conducts, turning on
inverted at U2-10 to turn on Q5. The resulting low at J7-22
DS3. Indicator DS8 remains lighted as previously discussed.
causes DS8 in the test set to light.
(11) Refer to step 10 in figure 2-8 and in the A9 test
(6) Refer to step 5 in figure 2-8 and in the A9 test
table. Pressing S11 causes the reset signal at J7-6 to go low.
table. The same basic connections are made for step 5 as for
The reset signal resets the relay drive 5 flip-flop and turns
step 4. When S11 is held, K8 is energized, which applies a
Q5 off. J7-22 goes high, which turns off DS8 in the test set.
low to the reset signal at J7-6. Refer to the A9 foldout
The high also deenergizes relays K1 and K2 on the card,
schematic from TM 9-1270-212-14&P. With U4 reset,
opening the circuits to DS3 and DS4, which go out.
U10-1 is low. The low is inverted to a logic high at U2-6,
which is coupled through J7-23 to Q7 in the test set. The
(12) Refer to step 11 in figure 2-8 and in the A9 test
high turns on Q7, causing DS1 to light.
table. Releasing S11 causes the reset signal at J7-6 to go
high but no count occurs because J7-11 and -13 are not
(7) Refer to step 6 in figure 2-8 and in the A9 test
held low. Therefore, DS3, DS4, and DS8 remain off.
table. When S11 is released, K8 deenergizes, which allows
the reset signal at J7-6 to go high. The high at J7-6 allows
the logic circuitry to count. Refer to the A9 foldout
2-15. Logic Card A10/A1 5 Test Theory.
schematic from TM 9-1270-212-14&P. As U10-1 goes high,
the high is inverted to a low at U2-6. The low at U2-6 is
NOTE
connected through J7-23 to turn off DS1. As the count
Unless otherwise indicated, the information in
continues and the signals at relay drives 1 through 9 are
grounded, one at a time, test set indicators DS3, DS4, DS5,
this paragraph applies equally to logic card
A10, used in the EIA from XM128, and logic
DS6, DS8, DS9, DS10, DS11, and DS12 light in sequence,
card Al5, used in the EIA from XM136. Where
about five indicators a second. When U10-13 goes low, the
signal nomenclature differs between the two
count stops and J7-16 goes high. The high at J7-26 lights
logic cards, the nomenclature for the logic card
DS13. The flip-flop associated with relay drive 5 keeps
J7-22 grounded, and DS8 remains lighted.
(A10) used in the EIA from XM128 is used as
the basic signal nomenclature, with the signal
(8) Refer to step 7 in figure 2-8 and in the A9 test
nomenclature for the other logic card (A15)
table. Setting S8 to position 6 maintains 5 volts dc at J7-1
following in parentheses.
through wiper 1 and contact 7 of S8-F. J7-11 and -13
remain grounded through contact 7 and wiper 1 of S8B;
a. Reference Material. The following reference materials
however, the skip signal at J7-24 is isolated by CR16 and
are required to support the logic card A10/A15 test theory
goes high. The high at J7-24 enables the skip function on
discussion:
the card. Pressing S11 energizes K8, applying a reset low at
(1) Logic-card-A10 or logic-card-A15 test table from
J7-6, which, in turn, causes J7-23 to go high as explained in
TM 9-1270-212-14&P
(6) above. DSl again lights.

Privacy Statement - Press Release - Copyright Information. - Contact Us

Integrated Publishing, Inc.
6230 Stone Rd, Unit Q Port Richey, FL 34668

Phone For Parts Inquiries: (727) 493-0744
Google +