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Supporting Documents.
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TM-9-4931-363-14-P Fire Control Subsystem Test Set AN/GSM-249 P/N 2201736-05 Manual
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Self-Test Theory.
TM 9-4931-363-14&P
Section II. POWER DISTRIBUTION AND SELF-TEST
2-3. Test Set Power Distribution.
d. Refer to the test set schematic (foldout FO-2, sheet
7). Stepdown transformer T1 supplies ac power to the
a. Refer to the test set schematic in foldout FO-2, sheet
individual rectifier circuits on power supply card A12. The
4. External power is connected to POWER connector J3.
primary winding at T1-1 is connected to S4-C, contacts 2
through 10, and the return at T1-2 is connected to the
Either a 60- or 400-Hz source of 115-volt, single-phase ac
400-Hz returns at ECP6. Therefore, Tl (and T2 and T3
power can be accepted; power cable W3 is to be used if the
power source is 60 Hz and power cable W4 is to be used if
also) are energized for all positions of the TEST SELECT
the power source is 400 Hz.
switch except the OFF position.
e. T1 provides a pair of 10-volt and a pair of 20-volt
b. Assume that power cable W3 is connected to a 60-Hz
inputs to power supply card A12 through pins XA12-24
power source. While POWER switch S1 is in the center OFF
and -16, and -4, -38 and 40, and -2 and -4, and -26 and -28,
position, no power is applied to the test set and POWER
respectively. The 10-volt transformer outputs are common
indicator DS18 is not lighted. When S1 is set to ON-60 HZ,
with connector J6 and connector XA12. The 20-volt
60-Hz power from J3-A is connected through fuse F1 and
transformer outputs pass through contacts of relays K9 and
through S1-1 and -2 to 28-volt dc unregulated power supply
K10, which, when deenergized, connect power to XAl2.
PS1-1. The return is connected from J3-B through S1-4 and
Refer to the power supply A12 card schematic (foldout
-5 to PS1-2. The +28 volts dc at PS1-3 is connected to
FO-4). The T1 outputs energize four full-wave bridge
POWER indicator DS18, lighting the indicator. The
rectifiers, the outputs of which are connected to solid-state
+28-volt dc power is also connected through line filter FL2
regulators AR1 through AR5. The regulators are
to 115-volt ac, 400-Hz inverter PS2-1. The 28-volt dc return
current-limited and thermally protected against overload.
is connected from PS1-4 to the connections listed for ECP7
on sheet 1 of the schematic, and through line filter FL1 to
f. Power supply card A12 contains test logic that
PS2-2. The output of the inverter is connected through
indicates the status of test set internal power. The 18-volt
S1-8 and -7 to the connections listed in ECP4. The inverter
dc output of AR1 is attenuated across divider network R1
returns are connected as shown in ECP6, which is common
and R2 and connected as a high to U1-2. The 12-volt dc
with ECP1. Should S1 be accidentally placed to ON-400
output of AR2 is attenuated across divider network R3 and
HZ with the 60-Hz power connected, nothing will happen.
R4 and connected as a high to U1-4. The 28-volt dc input
from chassis-mounted PS1 through S11 and S4-B-5 to
c. Assume that power cable W4 is connected to a
XA12-22 is attenuated across divider network R5 and R6
400-Hz power source. While POWER switch S1 is in the
and connected as a high to U1-1. The 10-volt ac input from
center OFF position, no power is applied to the test set and
chassis-mounted T2-1 (ECP8) to XA12-12 and T2-4 (ECP9)
POWER indicator DS18 is not lighted. When S1 is set to
to XA12-14 is rectified by diodes CR17 and CR18, is
ON-400 HZ, 400-Hz power from J3-D is connected through
attenuated and filtered by R9, R10, and C16, and is applied
fuse F2 and through S1-3 to -2 to 28-volt dc unregulated
as a high to U1-5. The three U2 inverters connected to
power supply PS1. PS1 accepts either 60-Hz or 400-Hz,
A12-6 form a wired OR gate. If the output of any inverter
115-volt power. The return is connected from J3-E through
goes low, it pulls the other outputs low also. Thus, if any
S1-6 and -5 to PS2-2. The +28 volts dc at PS1-3 is
input to U1 is low, U1-6 is high and U2-2 is low. The -6-
connected to POWER indicator DS18, lighting the
and -18-volt dc outputs are monitored with divider CR19,
R7, and CR20, and CR21, R8, and CR22. The voltage at
indicator. The +28-volt dc power is also connected through
line filter FL2 to 115-volt ac, 400-Hz inverter PS2-1. The
U2-3 and U2-5 is the diode junction drop, or about -0.7
+28-volt dc return is connected from PS1-4 to the
volt. R7 and R8 limit the current through 5.1-volt zener
connections listed for ECP7 on sheet 1 of the schematic
diodes CR19 and CR21. The lows at U2-3 and U2-5 are
and through line filter FL1 to PS2-2. The output of the
inverted to highs. Thus, if all monitored power sources are
inverter at PS2-4 is connected through S1-8 and -9 to the
normal, the power fail output at XA12-6 is high. The use of
the logic high is discussed in the theory of step 3 of the
connections listed in ECP4. Thus, the 400-Hz inverter is
active for 60- and 400-Hz inputs.

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